The present invention relates to a cache for context switching applications. More specifically, the invention relates to a cache for priority-based context switching in embedded processor systems, such as for use in networks.
Embedded processor systems often strive to eliminate the amount of off-chip memory required. Reducing off-chip memory typically reduces overall cost and valuable board area. Also, any reduction in the amount of off chip traffic will allow for improved throughput, as well as reduced power consumption. Increased memory demands for embedded processors often occur due to the need to add more and more functionality into tiny form factors.
Conventional embedded processor systems typically rely on instruction and non-instruction caches to reduce the amount of data traffic. Caches are typically on-chip random access memorys (RAMs), which contain frequently accessed data (instructions or non-instructions). When designed properly, caches are an excellent choice for reducing the amount of off-chip memory needed while at the same time not inhibiting performance.
However, conventional cache designs are not well suited for context switching applications. This is because the cache designs depend on locality of reference for good performance. Locality of reference refers to the property that future instructions (or non-instruction data) in the code stream come from a location near the current instruction fetch or data access. Therefore, there is a higher probability of a cache hit (i.e., having the next instruction fetch already in the cache). This is normally the case with conventional code streams, since execution order is largely sequential in nature and hence the cache can react effectively to this deterministic behavior.
In stark contrast, code that rapidly context switches reacts in a random non-deterministic way. A context switch may involve a code fetch from a completely different address, which is nowhere near the current instruction fetch. Often times when two or more processes cannot fit in the cache, thrashing may result. Thrashing is overhead caused by repeatedly replacing and restoring cached data to the main off-chip memory in a rapid fashion. Therefore, the processor will waste many central processor unit (CPU) cycles just to manage the cache and thus, will not be performing useful work. Caching in that regard can actually hurt performance and waste power due to the extreme overhead seen with fruitless cache updates.
Additionally, many applications have contexts that have different priorities. The caching of instructions may result in lower performance in many real time operating system environments for high priority contexts. A cache miss at an inopportune time can slow down the performance where high performance is crucial in order to achieve a real time response. The cache overhead of flushing and reading/writing cached data to keep it consistent and coherent with the memory system impacts overall system performance since cache updates waste network or bus bandwidth.
Accordingly, it would be beneficial to have innovative techniques for implementing a cache for context switching applications. Additionally, it would be beneficial if the cache could maintain high performance for high priority contexts in applications where the contexts can have different priorities.